William Bricken holds a multidisciplinary Ph.D. in Research Methods, Educational Psychology and Computer Science from Stanford University, and degrees in Statistics (MS Stanford), Education (Diploma of Education, Monash University Teacher's College, Australia), and Social Psychology (BA, UCLA). He has spent over 20 years developing the tools and techniques of Boundary Mathematics, and has also published widely in the fields of artificial intelligence, virtual reality, and education.
Bricken began his career as a Wizard at Atari’s Sunnyvale Research Lab, exploring advanced concepts in user interface.
As Principal Research Scientist at Advanced Decision Systems, he implemented the first high-performance Boundary Math inference engines, applying these tools to algebraic optimization of rule-bases, to reasoning in the presence of contradiction, to semantic debugging of programs, and to asynchronous parallel implementations of logical deduction.
As Distinguished Fellow and Director of the Autodesk Research Lab, Bricken and his team developed one of the first fully immersive virtual reality systems in the late 1980s.
He continued development of innovative software tools as Principal Scientist of University of Washington's Human Interface Technology Lab.
Beginning in 1993, at Interval Research Corporation, while contributing to a project to rebuild the foundations of computing, Bricken designed and implemented innovative algorithmic techniques for Boolean satisfiability, factoring and minimization, with applications to semiconductor logic synthesis and design optimization. Bricken's academic positions include Assistant Professor of Computer Science and Software Engineering at Seattle University, where he led the Masters of Software Engineering Program; and Research Associate Professor of Education and Research Associate Professor of Industrial Engineering at the University of Washington. In 2001, Bricken co-founded Bricken Technologies, a start-up company that focused on boundary logic algorithms for area and delay optimization, partitioning, abstraction, technology mapping, and performance parameterization of semiconductor designs.